The semiconductor industry is rapidly developing chips with smaller and smaller transistor dimensions to gain more functionality per unit area. As the dimensions of devices continue to shrink, so does the gap/space between the devices, increasing the difficulty to physically isolate the devices from one another. Filling in the high aspect ratio trenches/spaces/gaps between devices which are often irregularly shaped with high-quality dielectric materials is becoming an increasing challenge to implementation with existing methods including gapfill, hardmasks and spacer applications.
Integrated circuits are made possible by processes which produce intricately patterned material layers on substrate surfaces. Producing patterned materials on a substrate requires controlled methods for removal of exposed material. Chemical etching is used for a variety of purposes including transferring a pattern in photoresist into underlying layers, thinning layers or thinning lateral dimensions of features already present on the surface. Often it is desirable to have an etch process which etches one material faster than another helping, for example, pattern transfer processes. Such an etch process is said to be selective of the first material. As a result of the diversity of materials, circuits and processes, etch processes have been developed that selectively remove one or more of a broad range of materials.
Dry etch processes are often used for selectively removing material from semiconductor substrates. The dry etch process has the ability to gently remove material from miniature structures with minimal physical disturbance. Dry etch processes also allow the etch rate to be abruptly stopped by removing the gas phase reagents. Some dry-etch processes involve the exposure of a substrate to remote plasma by-products formed from one or more precursors. Many dry etch processes have recently been developed to selectively remove a variety of dielectrics relative to one another. However, relatively few dry-etch processes have been developed to selectively remove metal-containing materials. Methods are needed to broaden the process sequences to various metal-containing materials.
As the feature size of circuits and semiconductor devices keeps shrinking for higher integration density of electronic components, the self-aligned contact is becoming more and more attractive and highly required to solve increasingly-appeared patterning difficulties during via process. Generally, making the self-aligned contact needs bottom-up pillars, which however are very hard to be formed, especially when the material, shape, feature size, direction etc. are highly restricted. So far, most bottom-up pillars developed for self-aligned contacts are conductive metals, vertically aligned with submicron feature size and uncontrollable shapes.
Therefore, there is a need in the art for new methods for self-aligned patterning applications.